This invention relates to a video display system employing a flat X-Y matrix display panel and, more particularly, to such display apparatus which is of relatively simple construction, is far easier to assemble and is of lower cost than prior art apparatus.
Various proposals have been made for video display apparatus which include flat display panels in place of the usual cathode ray tube (CRT) now conventionally used in television receivers. The advantages of using a flat display panel are that a much more compact design can be attained, the overall television receiver can be constructed of solid state circuitry, the extremely high voltages commonly used in a CRT can be avoided, and others.
In operating a flat panel video display apparatus, a line of the received video signal is sampled a number of times during the line interval, and each sample is used to drive a corresponding display element associated with that line. Hence, depending upon the level of the sampled video signal, the intensity of the light emitted by the respective display elements will be of a corresponding brightness. Then, after one line interval is sampled, the next line is similarly sampled so as to correspondingly energize those display elements which are associated with the next line. This operation continues until a field or frame interval has been sampled and displayed.
In the foregoing example, each sample may be an analog sample, and complex analog switching techniques may be used to energize the appropriate display elements with the appropriate analog samples. It is through that generally better results can be achieved by driving the display elements in accordance with digital techniques. In one prior art flat panel display apparatus, the received video signal is sampled a number of times during a line interval, and each sample is digitized to, for example, an 8-bit word. The 8-bit word is transferred, for example, parallel-by-bit, to a memory which is capable of storing all of the 8-bit words which are produced during the sampling of the line interval. For example, 256 samples may be obtained, thus requiring a memory having a capacity to store 256 8-bit words.
Consistent with obtaining 256 samples during a line interval, the display panel may be comprised of a number of lines of display elements, each line containing 256 display elements. Once all of the samples for a line interval have been stored in the memory, they are read out to energize the corresponding display elements in a line of the display panel. Thus, sample No. 1 is read out to energize display element No. 1, sample No. 2 is read out to energize display element No. 2, and so on. Each 8-bit sample, when read out, must be effectively converted to a form whereby the brightness of the intensity of light emitted by the respective display elements is determined by the equivalent magnitude represented by the 8-bit word. This is attained by reading out each 8-bit word in a manner that is equivalent to pulse width modulation. Since each 8-bit word is constituted by bits of different bit levels ranging from the least significant bit to the most significant bit, those bits of lesser significance are read out from the memory with relatively short delays, while those bits of greater significance are read out with correspondingly greater delays. Hence, the duration that a display element is energized by a bit of greater significance, i.e., higher bit level, is far greater than the duration that the element is energized by a bit of lesser significance. The intensity of the light that is emitted by the element and perceived by a viewer appears greater if the element is energized for a longer duration.
Based upon the foregoing, the contents of the memory, which represents the digitized samples of one line interval of video signals, are read out in successive groups of bits, each group being constituted by 256 bits all of the same bit level. Furthermore, the rate at which these bits are read out of the memory changes, i.e., decreases, as the bit level increases. Hence, after all 256 8-bit words are stored in the memory, all of the least significant bit levels are read out in parallel, then all of the next more significant bits are read out in parallel, followed by all of the next more significant bits, and so on, until, finally, all of the most significant bits are read out in parallel. A temporary storage device, such as a latch circuit, may be provided to temporarily store the parallel bits which are read out, in succession, from the memory. Hence, the duration that each group of read out bits is stored is a function of the bit level of those bits. This results in pulse width modulation of the intensity of light emitted by the respective display elements in a line of the display panel, and is perceived as a brightness modulation by the viewer.
After one line of samples is read out of the memory, the next line is written in. Also, after all of the bits in the previous line have been used to energize the line of display elements of the display panel, the next line of display elements is enabled so that they can be energized in a similar manner. By enabling successive lines of display elements, a line-by-line raster is displayed, thereby forming a video picture corresponding to the video information contained in the received video signal.
In the flat panel display apparatus of the aforedescribed type, the samples stored in the memory cannot be read out therefrom until the memory has been filled, that is, until a line interval of video signals has been completely sampled. Also, write-in and read-out operations cannot be carried on simultaneously. Thus, in the prior art apparatus, video information is written into the memory during one line interval, and that information is read out from the memory during the next line interval. This means that only alternate line intervals are sampled and displayed. However, generally, this does not significantly detract from the quality of the video picture which ultimately is displayed. One problem, however, with this prior art apparatus, is that the memory typically is formed as a serial/parallel shift register, each stage of which is formed of about fifty circuit elements. Hence, the number of circuit elements which are needed to construct the shift register is about 256.times.8.times.50 which is in excess of 100,000. It is difficult to fabricate such a shift register as an integrated circuit. Accordingly, this shift register is formed of a number of individual circuit chips. However, the number of such chips is so large that it is not practical to mount them on the very same circuit board on which the display elements and associated drive circuitry are mounted. This means that the shift register is mounted on a separate circuit board and must be connected to the circuit board on which the display elements are mounted by individual conducting leads. Since the bits of the same bit level in all 256 samples are read out from the shift register in parallel, 256 individual conducting leads are needed to connect the circuit board on which the shift register is mounted to the circuit board on which the display elements are mounted. It is quite time-consuming, and thus expensive, to provide these 256 individual connections. Furthermore, it is relatively easy to misconnect one output terminal from one circuit board to another input terminal of the other circuit board. This, of course, can result in deleterious operation of the display apparatus.